As it is well known in this specific technical field, a standard Flash EEPROM memory device is integrated on semiconductor with a serial communication interface equipped with an input pin INPUT PAD, an output pin OUTPUT PAD, a system clock signal pin CK_PAD and some other control pins, like SELECT_PAD.
The block scheme, of FIG. 1 shows the most important memory device blocks and the SPI serial interface.
Up to now the serial interface of a non volatile Flash memory has been used in the applications according to a precise communication protocol. Another parallel interface has however been used almost exclusively in the device testing phase, in order to reduce the testing time.
Essentially, all the addresses and data being considered are used in the parallel mode, while only the clock signal CLK and the other four pins are necessary for the serial communication protocol.
The memory device receives through the input pin all protocol codes and all information concerning the addresses, the latter being parallelised by the SPI interface and brought to the flash memory through the address bus ADDR<20:0>.
Afterwards, for example in a reading operation, read data are forced by the Flash Core onto the data bus DBUS<15:0> and subsequently serialised and brought outside by means of the output pin.
The system clock scans the several protocol phases according to the timing sequence shown in FIG. 2.
As shown in this FIG. 2, the falling edge of the signal applied to the pin SELECT_PAD turns the memory device on and enables all input buffers, the first eight clock beats serve for the instruction code (Read, Write, etc.), the following twenty-four clock beats serve to move to the location address wished to be read or written, they follow therefore the beats required to synchronize the output data on OUTPUT_PAD.
The output bit number is not previously fixed but it can be set by the user through the SELECT_PAD, the last signal rising edge indicating the end of a reading operation.
At present, the testing flux software at both EWS (on-wafer-testing) and Final Test (assembled device testing) level has been conceived for a parallel-mode operation.
The need to produce low-cost packages leads inevitably to the reduction of the external pin number with subsequent need for a new testing flow, resulting therefore in devices having externally only the pins required by the serial communication mode with the corresponding and necessary control pins for this mode.
There are devices allowing to perform reading/writing operations on flash memories by using a system clock signal scanning the phases of a precise communication protocol at working frequencies of 25 MHz.
One of the great disadvantages in the development and industrialization of this kind of devices is the cost in terms of testing time especially in the EWS phase.
In fact, the whole flux serial execution involves a considerable waste of time.
The technical problem underlying embodiments of the present invention is to provide a non volatile Flash memory architecture equipped with an input/output interface, particularly for SPI serial communication protocol applications, having such structural and functional characteristics as to allow a fast and low-cost testing flux operating yet in the serial mode.